`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////
////                                                              //// 
////                                                              //// 
////  Parte del proyecto del simple comprobador de memoria        ////  
////                                                              ////
////                                                              //// 
////  Description                                                 //// 
////   - Memoria del sistema                                      //// 
////                                                              //// 
////  To Do:                                                      //// 
////   - Memoria donde se leen y se escriben los datos            //// 
////                                                              //// 
////  Author(s):                                                  //// 
////      - Sergio Gonzalez Q, sergiogq@hotmail.es                ////
////      - Alejandro Morales, ale3191@gmail.com                  //// 
////                                                              //// 
////////////////////////////////////////////////////////////////////// 
////                                                              //// 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 //// 
////                                                              //// 
//// This source file may be used and distributed without         //// 
//// restriction provided that this copyright statement is not    //// 
//// removed from the file and that any derivative work contains  //// 
//// the original copyright notice and the associated disclaimer. //// 
////                                                              //// 
//// This source file is free software; you can redistribute it   //// 
//// and/or modify it under the terms of the GNU Lesser General   //// 
//// Public License as published by the Free Software Foundation; //// 
//// either version 2.1 of the License, or (at your option) any   //// 
//// later version.                                               //// 
////                                                              //// 
//// This source is distributed in the hope that it will be       //// 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   //// 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //// 
//// PURPOSE.  See the GNU Lesser General Public License for more //// 
//// details.                                                     //// 
////                                                              //// 
//// You should have received a copy of the GNU Lesser General    //// 
//// Public License along with this source; if not, download it   //// 
//// from http://www.opencores.org/lgpl.shtml                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////


module MemorySRAM(clk_i,address_i,write_enable_i,output_enable_i,chip_select1_i,chip_select2_i,data_io);

	// Input
	input write_enable_i,clk_i; // write
	input output_enable_i; // read
	input chip_select1_i; // selects
	input chip_select2_i;
	input [3:0] address_i; // Address
	
	// Data bidirectional
	inout [7:0] data_io;

	// Memory
	reg [7:0] memory [15:0];
	
	// If this not reading puts impedance
	assign data_io = (!chip_select1_i && chip_select2_i && !output_enable_i && write_enable_i) ? memory[address_i] : 8'bz; 

	always @(posedge clk_i) // Change 
		
		if (!chip_select1_i && chip_select2_i && !write_enable_i && output_enable_i) // writing
			memory[address_i] = data_io;
	
endmodule
